A 4.2–373 K Functional 800-MS/s 12-b Buffer-Then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC With Integrated Active-Hold Technique

This article presents a source-follower (SF) and charge-pump (CP)-based amplification that is linear and bias-calibration-free across a wide temperature range from 4.2 to 373 K, targeting pipelined analog-to-digital converters (ADCs). While prior SF and CP-based amplifiers suffer from poor linearity because the SF must drive large amplified signals, we propose a buffer-then-amplify (BTA) CP architecture that relocates the CP to the SF output. As a result, the SF only buffers unamplified small-swing residues, fully exploiting its intrinsic linearity and eliminating the need for high-order gain calibrations even in advanced process nodes. To further enhance robustness and efficiency, we introduce an adaptively biased class-AB SF. An integrated active-hold technique is also proposed to eliminate the timing and bandwidth mismatch between the first-pipeline-stage sampling capacitor and the sub-ADC by repurposing the SF as a hold buffer for the sub-ADC. The prototype 12-bit 800-MS/s pipelined time-interleaved successive approximation register (TI-SAR) ADC is fabricated in 12-nm FinFET technology. It achieves SNDR higher than 55.0 dB across the 4.2–373 K temperature range with 40-MHz input, and peak Walden figure-of-merit (FoM_W) of 9.2 fJ/c.-step at 4.2 K. To the best of the authors’ knowledge, the achieved functional temperature range is the widest among >10-bit >300-MS/s ADCs.