A 65nm Cryogenic CMOS Design and Performance at 4.2K for Quantum State Controller Application

Engineering

• Electric Power Utilization 33%
• Integrated Circuit 33%
• Interconnects 100%
• Joule Heating Effect 66%
• Quantum State 100%
• Room Temperature 33%
• Significant Change 33%
• Simulation Program 33%
• Simulation Result 33%

Keyphrases

• Back-end-of-line 100%
• Cryogenic Characteristics 50%
• Interconnect Resistance 50%
• Line Resistance 50%
• RC Interconnect 50%
• Resistance Heating 50%

Chemical Engineering

• Cryogenics 100%
• Joule Heating 66%