A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS

Yanfei Chen; Sanroku Tsukamoto; Tadahiro Kuroda

doi:10.1109/ASSCC.2009.5357199

A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS

Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda

研究成果: Conference contribution

50 被引用数 (Scopus)

抄録

A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm². A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.

本文言語	English
ホスト出版物のタイトル	Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
ページ	145-148
ページ数	4
DOI	https://doi.org/10.1109/ASSCC.2009.5357199
出版ステータス	Published - 2009 12月 1
イベント	2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan, Province of China 継続期間: 2009 11月 16 → 2009 11月 18

出版物シリーズ

名前	Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Conference

Conference	2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
国/地域	Taiwan, Province of China
City	Taipei
Period	09/11/16 → 09/11/18

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

UN SDG

この成果は、次の持続可能な開発目標に貢献しています

文献へのアクセス

10.1109/ASSCC.2009.5357199

他のファイルとリンク

引用スタイル

Chen, Y, Tsukamoto, S & Kuroda, T 2009, A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS. in Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009., 5357199, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009, pp. 145-148, 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009, Taipei, Taiwan, Province of China, 09/11/16. https://doi.org/10.1109/ASSCC.2009.5357199

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N2 - A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.

AB - A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.

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A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS

抄録

出版物シリーズ

Conference

ASJC Scopus subject areas

UN SDG

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