TY - GEN
T1 - A configuration data multicasting method for coarse-grained reconfigurable architectures
AU - Kojima, Takuya
AU - Amano, Hideharu
N1 - Funding Information:
ACKNOWLEDGMENT This work is partially supported by JSPS KAKENHI S Grant Number 25220002 and JSPS KAKENHI B Grant Number 18H03215. This work is supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Synopsys, Inc and Cadence Design Systems, Inc.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/11/9
Y1 - 2018/11/9
N2 - This paper proposes a novel configuration data compression technique for coarse-grained reconfigurable architectures (CGRAs). The proposed technique is based on a multicast configuration technique called RoMultiC, which reduces the configuration time by multicasting the same data to multiple PEs(Processing Elements) with two bit-maps. Scheduling algorithms for an optimizing the order of multicasting have been proposed. In general, configuration data for CGRAs can be divided into some fields like machine code formats. The proposed scheme confines a part of fields for multicasting so that the possibility of multicasting more PEs can be increased. This paper analyzes algorithms to find a configuration pattern which maximizes the number of multicasted PEs. We implemented the proposed scheme to CMA (Cool Mega Array), a straight forward CGRA as a case study. Experimental results show that the proposed method achieves 40.0% smaller configuration for an image processing application at maximum. Furthermore, it achieves 35.6% reduction of the power consumption for the configuration with a negligible area overhead.
AB - This paper proposes a novel configuration data compression technique for coarse-grained reconfigurable architectures (CGRAs). The proposed technique is based on a multicast configuration technique called RoMultiC, which reduces the configuration time by multicasting the same data to multiple PEs(Processing Elements) with two bit-maps. Scheduling algorithms for an optimizing the order of multicasting have been proposed. In general, configuration data for CGRAs can be divided into some fields like machine code formats. The proposed scheme confines a part of fields for multicasting so that the possibility of multicasting more PEs can be increased. This paper analyzes algorithms to find a configuration pattern which maximizes the number of multicasted PEs. We implemented the proposed scheme to CMA (Cool Mega Array), a straight forward CGRA as a case study. Experimental results show that the proposed method achieves 40.0% smaller configuration for an image processing application at maximum. Furthermore, it achieves 35.6% reduction of the power consumption for the configuration with a negligible area overhead.
KW - CGRA
KW - Espresso
KW - ILP
KW - configuration data reduction
KW - reconfigurable architecture
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U2 - 10.1109/FPL.2018.00048
DO - 10.1109/FPL.2018.00048
M3 - Conference contribution
AN - SCOPUS:85060307886
T3 - Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018
SP - 239
EP - 242
BT - Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 28th International Conference on Field-Programmable Logic and Applications, FPL 2018
Y2 - 26 August 2018 through 30 August 2018
ER -