A Cryo-CMOS Fractional-N PLL in 22 nm FDSOI Operating at 6 K for Trapped-Ion Quantum Computer Applications

Yazan Saad-Aldine; Adilet Dossanov; Alexander Meyer; Kaoru Yamashita; Hiroki Ishikuro; Vadim Issakov

doi:10.1109/LMWT.2026.3677613

A Cryo-CMOS Fractional-N PLL in 22 nm FDSOI Operating at 6 K for Trapped-Ion Quantum Computer Applications

Yazan Saad-Aldine
, Adilet Dossanov
, Alexander Meyer
, Kaoru Yamashita
, Hiroki Ishikuro
, Vadim Issakov

電気情報工学科

研究成果: Article › 査読

抄録

This letter presents a fractional-N charge-pump phase-locked loop (CP-PLL) operating at cryogenic temperatures (CT) down to 6 K. The phase-locked loop (PLL), generating signals in the frequency range around 2.28–2.68 GHz, is intended as a reference source in a microwave signal generator for a trapped-ion quantum computer operating with ⁹Be⁺ ions. Using a third-order MASH DSmodulator (DSM), the PLL achieves a highly competitive FoM of −245 dB. The circuit exhibits the highest fractional spur suppression among the recently reported cryogenic PLLs, as well as the lowest chip area.

本文言語	English
ページ（範囲）	890-893
ページ数	4
ジャーナル	IEEE Microwave and Wireless Technology Letters
巻	36
号	6
DOI	https://doi.org/10.1109/LMWT.2026.3677613
出版ステータス	Published - 2026 6月 1

ASJC Scopus subject areas

凝縮系物理学
電子工学および電気工学

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10.1109/LMWT.2026.3677613

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title = "A Cryo-CMOS Fractional-N PLL in 22 nm FDSOI Operating at 6 K for Trapped-Ion Quantum Computer Applications",

abstract = "This letter presents a fractional-N charge-pump phase-locked loop (CP-PLL) operating at cryogenic temperatures (CT) down to 6 K. The phase-locked loop (PLL), generating signals in the frequency range around 2.28{\textendash}2.68 GHz, is intended as a reference source in a microwave signal generator for a trapped-ion quantum computer operating with 9Be+ ions. Using a third-order MASH DSmodulator (DSM), the PLL achieves a highly competitive FoM of −245 dB. The circuit exhibits the highest fractional spur suppression among the recently reported cryogenic PLLs, as well as the lowest chip area.",

keywords = "Cryo-CMOS, cryogenic electronics, microwave source, phase-locked loop (PLL), qubits, scalability, trapped-ion",

author = "Yazan Saad-Aldine and Adilet Dossanov and Alexander Meyer and Kaoru Yamashita and Hiroki Ishikuro and Vadim Issakov",

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AU - Saad-Aldine, Yazan

AU - Dossanov, Adilet

AU - Meyer, Alexander

AU - Yamashita, Kaoru

AU - Ishikuro, Hiroki

AU - Issakov, Vadim

PY - 2026/6/1

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N2 - This letter presents a fractional-N charge-pump phase-locked loop (CP-PLL) operating at cryogenic temperatures (CT) down to 6 K. The phase-locked loop (PLL), generating signals in the frequency range around 2.28–2.68 GHz, is intended as a reference source in a microwave signal generator for a trapped-ion quantum computer operating with 9Be+ ions. Using a third-order MASH DSmodulator (DSM), the PLL achieves a highly competitive FoM of −245 dB. The circuit exhibits the highest fractional spur suppression among the recently reported cryogenic PLLs, as well as the lowest chip area.

AB - This letter presents a fractional-N charge-pump phase-locked loop (CP-PLL) operating at cryogenic temperatures (CT) down to 6 K. The phase-locked loop (PLL), generating signals in the frequency range around 2.28–2.68 GHz, is intended as a reference source in a microwave signal generator for a trapped-ion quantum computer operating with 9Be+ ions. Using a third-order MASH DSmodulator (DSM), the PLL achieves a highly competitive FoM of −245 dB. The circuit exhibits the highest fractional spur suppression among the recently reported cryogenic PLLs, as well as the lowest chip area.

KW - Cryo-CMOS

KW - cryogenic electronics

KW - microwave source

KW - phase-locked loop (PLL)

KW - qubits

KW - scalability

KW - trapped-ion

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A Cryo-CMOS Fractional-N PLL in 22 nm FDSOI Operating at 6 K for Trapped-Ion Quantum Computer Applications

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