TY - GEN
T1 - A Dual-Mode 2:1 Switched Capacitor Converter with >65% Efficiency over 1000x Load Current Range and One Clock Cycle Transient Response
AU - Tan, Yi
AU - Ishikuro, Hiroki
N1 - Funding Information:
ACKNOWLEDGMENT This work is supported by JST Support for Pioneering Research Initiated by the Next Generation (SPRING), Grant Number JPMJSP2123.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This work presents a fully-integrated switched-capacitor dc-dc design with consistent power conversion efficiency in wide-load current range and active transient response. A fully-integrated centralized dual-lower-bound hysteresis controller with delay compensation techniques is proposed and implemented in 180-nm technology to extend the maximum load current. A dual-mode design provides a flexible trade-off between ripple and speed reduced sampling frequency and more phases. With power-frequency scaling, a consistent efficiency overall >1000x load-current range, which is measured to have >65% efficiency from 5.3 µW to 6.9 mW, is guaranteed. Meanwhile, a 1 clock cycle transient response time is achieved by state-detection in frequency control, which can be further improved by providing external activation signal at system level. As power consumption decreases and capacitor density increases with advanced technology nodes, this approach is expected to provide a competitive approach with its consistent performance over wide load current range.
AB - This work presents a fully-integrated switched-capacitor dc-dc design with consistent power conversion efficiency in wide-load current range and active transient response. A fully-integrated centralized dual-lower-bound hysteresis controller with delay compensation techniques is proposed and implemented in 180-nm technology to extend the maximum load current. A dual-mode design provides a flexible trade-off between ripple and speed reduced sampling frequency and more phases. With power-frequency scaling, a consistent efficiency overall >1000x load-current range, which is measured to have >65% efficiency from 5.3 µW to 6.9 mW, is guaranteed. Meanwhile, a 1 clock cycle transient response time is achieved by state-detection in frequency control, which can be further improved by providing external activation signal at system level. As power consumption decreases and capacitor density increases with advanced technology nodes, this approach is expected to provide a competitive approach with its consistent performance over wide load current range.
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U2 - 10.1109/ICECS202256217.2022.9971001
DO - 10.1109/ICECS202256217.2022.9971001
M3 - Conference contribution
AN - SCOPUS:85145354078
T3 - ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
BT - ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022
Y2 - 24 October 2022 through 26 October 2022
ER -