A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 × 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.
|ジャーナル||Proceedings of the Custom Integrated Circuits Conference|
|出版ステータス||Published - 2008|
|イベント||IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States|
継続期間: 2008 9月 21 → 2008 9月 24
ASJC Scopus subject areas