TY - JOUR
T1 - A dynamic offset control technique for comparator design in scaled CMOS technology
AU - Zhu, Xiaolei
AU - Chen, Yanfei
AU - Kibune, Masaya
AU - Tomita, Yasumoto
AU - Hamada, Takayuki
AU - Tamura, Hirotaka
AU - Tsukamoto, Sanroku
AU - Kuroda, Tadahiro
PY - 2008
Y1 - 2008
N2 - A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 × 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.
AB - A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 × 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.
UR - http://www.scopus.com/inward/record.url?scp=57849102144&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=57849102144&partnerID=8YFLogxK
U2 - 10.1109/CICC.2008.4672130
DO - 10.1109/CICC.2008.4672130
M3 - Conference article
AN - SCOPUS:57849102144
SN - 0886-5930
SP - 495
EP - 498
JO - Proceedings of the Custom Integrated Circuits Conference
JF - Proceedings of the Custom Integrated Circuits Conference
M1 - 4672130
T2 - IEEE 2008 Custom Integrated Circuits Conference, CICC 2008
Y2 - 21 September 2008 through 24 September 2008
ER -