A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Naomi Seki; Lei Zhao; Jo Kei; Daisuke Ikebuchi; Yu Kojima; Yohei Hasegawa; Hideharu Amano; Kashima Toshihiro Kashima; Seidai Takeda; Toshiaki Shirai; Mitustaka Nakata; Kimiyoshi Usami; Tetsuya Sunata; Jun Kanai; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura

doi:10.1109/ICCD.2008.4751924

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Kashima Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitustaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura

情報工学科

研究成果: Conference contribution

36 被引用数 (Scopus)

抄録

A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and Translation Lookaside Buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.

本文言語	English
ホスト出版物のタイトル	26th IEEE International Conference on Computer Design 2008, ICCD
ページ	612-617
ページ数	6
DOI	https://doi.org/10.1109/ICCD.2008.4751924
出版ステータス	Published - 2008
イベント	26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA, United States 継続期間: 2008 10月 12 → 2008 10月 15

出版物シリーズ

名前	26th IEEE International Conference on Computer Design 2008, ICCD

Other

Other	26th IEEE International Conference on Computer Design 2008, ICCD
国/地域	United States
City	Lake Tahoe, CA
Period	08/10/12 → 08/10/15

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

文献へのアクセス

10.1109/ICCD.2008.4751924

他のファイルとリンク

引用スタイル

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M., & Nakamura, H. (2008). A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000. In 26th IEEE International Conference on Computer Design 2008, ICCD (pp. 612-617). 記事 4751924 (26th IEEE International Conference on Computer Design 2008, ICCD). https://doi.org/10.1109/ICCD.2008.4751924

Seki, N, Zhao, L, Kei, J, Ikebuchi, D, Kojima, Y, Hasegawa, Y, Amano, H, Toshihiro Kashima, K, Takeda, S, Shirai, T, Nakata, M, Usami, K, Sunata, T, Kanai, J, Namiki, M, Kondo, M & Nakamura, H 2008, A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000. in 26th IEEE International Conference on Computer Design 2008, ICCD., 4751924, 26th IEEE International Conference on Computer Design 2008, ICCD, pp. 612-617, 26th IEEE International Conference on Computer Design 2008, ICCD, Lake Tahoe, CA, United States, 08/10/12. https://doi.org/10.1109/ICCD.2008.4751924

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abstract = "A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and Translation Lookaside Buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.",

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AU - Seki, Naomi

AU - Zhao, Lei

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AU - Ikebuchi, Daisuke

AU - Kojima, Yu

AU - Hasegawa, Yohei

AU - Amano, Hideharu

AU - Toshihiro Kashima, Kashima

AU - Takeda, Seidai

AU - Shirai, Toshiaki

AU - Nakata, Mitustaka

AU - Usami, Kimiyoshi

AU - Sunata, Tetsuya

AU - Kanai, Jun

AU - Namiki, Mitaro

AU - Kondo, Masaaki

AU - Nakamura, Hiroshi

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AB - A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and Translation Lookaside Buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.

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A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

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