A High-Speed 8-Bit Single-Channel SAR ADC with Tailored Bit Intervals and Split Capacitors †

As wireless communication systems continue to demand higher data transmission rates, the need for analog-to-digital converters (ADCs) with a higher sampling rate becomes increasingly critical. However, traditional successive approximation register (SAR) ADCs operating at 1 bit/cycle often face speed limitations due to the fixed bit intervals and comparator regeneration delays, which constrain their scalability in advanced technology nodes. To address these challenges, this paper presents a high-speed 8-bit single-channel SAR ADC featuring a novel delay generation circuit that enables tailored bit intervals (TBIs) to reduce conversion latency. A split capacitive digital-to-analog converter (CDAC) is employed to suppress input common-mode voltage shifts, while inverted dynamic latch pairs and early capacitor reset techniques are introduced to improve conversion speed. The proposed ADC is implemented in a 16 nm CMOS process, occupying only 0.0012 mm². Post-layout simulations across extreme process and temperature corners validate the robustness of the design. The TBI-ADC achieves an effective number of bits (ENOB) of 7.20 bits at Typical–Typical (TT) 25 °C with a power consumption of 6.94 mW. Furthermore, it reaches a sampling rate of 1.6 GS/s at Fast–Fast (FF) −40 °C, representing a 33% improvement over the fastest previously reported single-channel, 1 bit/cycle, 8-bit SAR ADC.