A High-Speed Low-Power Two-Stage Comparator with Regeneration Enhancement and Through Current Suppression Techniques

Chia Wei Pai, Hiroki Ishikuro

研究成果: Conference contribution

抄録

This paper presents a high-speed low-power two-stage dynamic comparator for SAR ADC. The pre-amplifier of the proposed comparator uses the dynamic bias technique to save power. To increase the output voltage difference of the pre-amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback ability. The tail current source is replaced by the input pair to save power. The auxiliary input pair speeds up the regeneration of the latch. Simulation results demonstrate that the proposed comparator with VDD=1.8 V achieved a clock-to-Q delay of 228 ps and an input-referred noise of 479 μ V at Vid=1 mV and VCM= 0.9 V. The proposed comparator consumes 196.3 fJ per comparison with 1.024 GHz.

本文言語English
ホスト出版物のタイトル2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
出版社Institute of Electrical and Electronics Engineers Inc.
ページ79-83
ページ数5
ISBN(電子版)9798350302103
DOI
出版ステータスPublished - 2023
イベント2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 - Tempe, United States
継続期間: 2023 8月 62023 8月 9

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
ISSN(印刷版)1548-3746

Conference

Conference2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
国/地域United States
CityTempe
Period23/8/623/8/9

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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