A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections

Shinji Nishimura; Tomohiro Kudoh; Hiroaki Nishi; Katsuyoshi Harasawa; Nobuhiro Matsudaira; Shigeto Akutsu; Koji Tasyo; Hideharu Amano

doi:10.1109/PI.1999.806389

A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections

Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Katsuyoshi Harasawa, Nobuhiro Matsudaira, Shigeto Akutsu, Koji Tasyo, Hideharu Amano

情報工学科

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A large throughput, low latency network switch (RHiNET-2/SW) has been developed for a distributed parallel computing system. This switch has a new architecture to support low latency "zero-copy" communication in multi-tasking environments. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a CMOS ASIC switch are implemented on a compact circuit board. To achieve large-throughput (64 Gbit/s) and low-latency network performance, the SW-LSI has a customized high-speed LVDS I/O interface, and high-speed internal SRAM memory in a 784-pin-BGA one-chip package. Also, we have developed the device implementation technologies to overcome the electrical problems (crosstalk, skew, reflection and noise). These implementation technologies are applicable for switches used in other high-speed networks such as GSN, 4 Gbit/s Fiber Channel or 10 Gbit/s Ethernet.

本文言語	English
ホスト出版物のタイトル	Proceedings - 6th International Conference on Parallel Interconnects, PI 1999
編集者	Eugen Schenfeld, Ray Kostuk, Craig Lund, Michael Haney
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	5-12
ページ数	8
ISBN（電子版）	076950440X, 9780769504407
DOI	https://doi.org/10.1109/PI.1999.806389
出版ステータス	Published - 1999
イベント	6th International Conference on Parallel Interconnects, PI 1999 - Anchorage, United States 継続期間: 1999 10月 17 → 1999 10月 19

出版物シリーズ

名前	Proceedings - 6th International Conference on Parallel Interconnects, PI 1999

Other

Other	6th International Conference on Parallel Interconnects, PI 1999
国/地域	United States
City	Anchorage
Period	99/10/17 → 99/10/19

ASJC Scopus subject areas

コンピュータネットワークおよび通信
ハードウェアとアーキテクチャ

文献へのアクセス

10.1109/PI.1999.806389

他のファイルとリンク

フィンガープリント

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引用スタイル

Nishimura, S., Kudoh, T., Nishi, H., Harasawa, K., Matsudaira, N., Akutsu, S., Tasyo, K., & Amano, H. (1999). A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections. In E. Schenfeld, R. Kostuk, C. Lund, & M. Haney (Eds.), Proceedings - 6th International Conference on Parallel Interconnects, PI 1999 (pp. 5-12). 記事 806389 (Proceedings - 6th International Conference on Parallel Interconnects, PI 1999). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PI.1999.806389

A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections. / Nishimura, Shinji; Kudoh, Tomohiro; Nishi, Hiroaki その他.
Proceedings - 6th International Conference on Parallel Interconnects, PI 1999. ed. / Eugen Schenfeld; Ray Kostuk; Craig Lund; Michael Haney. Institute of Electrical and Electronics Engineers Inc., 1999. p. 5-12 806389 (Proceedings - 6th International Conference on Parallel Interconnects, PI 1999).

研究成果: Conference contribution

Nishimura, S, Kudoh, T, Nishi, H, Harasawa, K, Matsudaira, N, Akutsu, S, Tasyo, K & Amano, H 1999, A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections. in E Schenfeld, R Kostuk, C Lund & M Haney (eds), Proceedings - 6th International Conference on Parallel Interconnects, PI 1999., 806389, Proceedings - 6th International Conference on Parallel Interconnects, PI 1999, Institute of Electrical and Electronics Engineers Inc., pp. 5-12, 6th International Conference on Parallel Interconnects, PI 1999, Anchorage, United States, 99/10/17. https://doi.org/10.1109/PI.1999.806389

Nishimura S, Kudoh T, Nishi H, Harasawa K, Matsudaira N, Akutsu S その他. A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections. In Schenfeld E, Kostuk R, Lund C, Haney M, editors, Proceedings - 6th International Conference on Parallel Interconnects, PI 1999. Institute of Electrical and Electronics Engineers Inc. 1999. p. 5-12. 806389. (Proceedings - 6th International Conference on Parallel Interconnects, PI 1999). doi: 10.1109/PI.1999.806389

Nishimura, Shinji ; Kudoh, Tomohiro ; Nishi, Hiroaki その他. / A network switch using optical interconnection for high performance parallel computing using PCs : High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections. Proceedings - 6th International Conference on Parallel Interconnects, PI 1999. editor / Eugen Schenfeld ; Ray Kostuk ; Craig Lund ; Michael Haney. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 5-12 (Proceedings - 6th International Conference on Parallel Interconnects, PI 1999).

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abstract = "A large throughput, low latency network switch (RHiNET-2/SW) has been developed for a distributed parallel computing system. This switch has a new architecture to support low latency {"}zero-copy{"} communication in multi-tasking environments. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a CMOS ASIC switch are implemented on a compact circuit board. To achieve large-throughput (64 Gbit/s) and low-latency network performance, the SW-LSI has a customized high-speed LVDS I/O interface, and high-speed internal SRAM memory in a 784-pin-BGA one-chip package. Also, we have developed the device implementation technologies to overcome the electrical problems (crosstalk, skew, reflection and noise). These implementation technologies are applicable for switches used in other high-speed networks such as GSN, 4 Gbit/s Fiber Channel or 10 Gbit/s Ethernet.",

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