A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Isamu Hayashi; Takeshi Matsubara; Satoshi Kumaki; Abul Hasan Johari; Hiroki Ishikuro; Tadahiro Kuroda

doi:10.1109/ASSCC.2010.5716596

A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Isamu Hayashi, Takeshi Matsubara, Satoshi Kumaki, Abul Hasan Johari, Hiroki Ishikuro, Tadahiro Kuroda

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

本文言語	English
ホスト出版物のタイトル	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
ページ	225-228
ページ数	4
DOI	https://doi.org/10.1109/ASSCC.2010.5716596
出版ステータス	Published - 2010 12月 1
イベント	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China 継続期間: 2010 11月 8 → 2010 11月 10

出版物シリーズ

名前	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Other

Other	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
国/地域	China
City	Beijing
Period	10/11/8 → 10/11/10

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

文献へのアクセス

10.1109/ASSCC.2010.5716596

他のファイルとリンク

引用スタイル

Hayashi, I., Matsubara, T., Kumaki, S., Johari, A. H., Ishikuro, H., & Kuroda, T. (2010). A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 225-228). 記事 5716596 (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010). https://doi.org/10.1109/ASSCC.2010.5716596

Hayashi, I, Matsubara, T, Kumaki, S, Johari, AH, Ishikuro, H & Kuroda, T 2010, A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. in 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716596, 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp. 225-228, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 10/11/8. https://doi.org/10.1109/ASSCC.2010.5716596

@inproceedings{ee8b3972052347d08f1a11624a0e322c,

title = "A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V",

abstract = "A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).",

author = "Isamu Hayashi and Takeshi Matsubara and Satoshi Kumaki and Johari, {Abul Hasan} and Hiroki Ishikuro and Tadahiro Kuroda",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/ASSCC.2010.5716596",

language = "English",

isbn = "9781424482979",

series = "2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010",

pages = "225--228",

booktitle = "2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010",

note = "2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 ; Conference date: 08-11-2010 Through 10-11-2010",

}

TY - GEN

T1 - A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

AU - Hayashi, Isamu

AU - Matsubara, Takeshi

AU - Kumaki, Satoshi

AU - Johari, Abul Hasan

AU - Ishikuro, Hiroki

AU - Kuroda, Tadahiro

PY - 2010/12/1

Y1 - 2010/12/1

N2 - A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

AB - A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

UR - http://www.scopus.com/inward/record.url?scp=79952850912&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79952850912&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2010.5716596

DO - 10.1109/ASSCC.2010.5716596

M3 - Conference contribution

AN - SCOPUS:79952850912

SN - 9781424482979

T3 - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

SP - 225

EP - 228

BT - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

T2 - 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Y2 - 8 November 2010 through 10 November 2010

ER -

A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

抄録

出版物シリーズ

Other

ASJC Scopus subject areas

文献へのアクセス

他のファイルとリンク

フィンガープリント

引用スタイル