A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Yoshinori Kohama; Yasufumi Sugimori; Shotaro Saito; Yohei Hasegawa; Toru Sano; Kazutaka Kasuga; Yoichi Yoshida; Kiichi Niitsu; Noriyuki Miura; Hideharu Amano; Tadahiro Kuroda

A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Yoshinori Kohama, Yasufumi Sugimori, Shotaro Saito, Yohei Hasegawa, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Hideharu Amano, Tadahiro Kuroda

情報工学科

研究成果: Conference contribution

15 被引用数 (Scopus)

抄録

This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.

本文言語	English
ホスト出版物のタイトル	2009 Symposium on VLSI Circuits
ページ	94-95
ページ数	2
出版ステータス	Published - 2009 11月 18
イベント	2009 Symposium on VLSI Circuits - Kyoto, Japan 継続期間: 2009 6月 16 → 2009 6月 18

出版物シリーズ

名前	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2009 Symposium on VLSI Circuits
国/地域	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

他のファイルとリンク

引用スタイル

Kohama, Y, Sugimori, Y, Saito, S, Hasegawa, Y, Sano, T, Kasuga, K, Yoshida, Y, Niitsu, K, Miura, N, Amano, H & Kuroda, T 2009, A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. in 2009 Symposium on VLSI Circuits., 5205288, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 94-95, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09/6/16.

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title = "A scalable 3D processor by homogeneous chip stacking with inductive-coupling link",

abstract = "This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.",

author = "Yoshinori Kohama and Yasufumi Sugimori and Shotaro Saito and Yohei Hasegawa and Toru Sano and Kazutaka Kasuga and Yoichi Yoshida and Kiichi Niitsu and Noriyuki Miura and Hideharu Amano and Tadahiro Kuroda",

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AU - Kohama, Yoshinori

AU - Sugimori, Yasufumi

AU - Saito, Shotaro

AU - Hasegawa, Yohei

AU - Sano, Toru

AU - Kasuga, Kazutaka

AU - Yoshida, Yoichi

AU - Niitsu, Kiichi

AU - Miura, Noriyuki

AU - Amano, Hideharu

AU - Kuroda, Tadahiro

PY - 2009/11/18

Y1 - 2009/11/18

N2 - This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.

AB - This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.

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M3 - Conference contribution

AN - SCOPUS:70449427842

SN - 9784863480018

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

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EP - 95

BT - 2009 Symposium on VLSI Circuits

T2 - 2009 Symposium on VLSI Circuits

Y2 - 16 June 2009 through 18 June 2009

ER -

A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

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ASJC Scopus subject areas

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