抄録
This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.
| 本文言語 | English |
|---|---|
| ページ(範囲) | 2741-2749 |
| ページ数 | 9 |
| ジャーナル | IEICE Transactions on Communications |
| 巻 | E85-B |
| 号 | 12 |
| 出版ステータス | Published - 2002 12月 |
| 外部発表 | はい |
ASJC Scopus subject areas
- ソフトウェア
- コンピュータ ネットワークおよび通信
- 電子工学および電気工学
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