A versatile recognition processor for sensor network applications

Risako Takashima; Yuya Hanai; Yuichi Hori; Tadahiro Kuroda

doi:10.1109/ASPDAC.2010.5419867

A versatile recognition processor for sensor network applications

Risako Takashima
, Yuya Hanai
, Yuichi Hori
, Tadahiro Kuroda

研究成果: Conference contribution

抄録

A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.

本文言語	English
ホスト出版物のタイトル	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
ページ	349-350
ページ数	2
DOI	https://doi.org/10.1109/ASPDAC.2010.5419867
出版ステータス	Published - 2010 4月 28
イベント	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China 継続期間: 2010 1月 18 → 2010 1月 21

出版物シリーズ

名前	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
国/地域	Taiwan, Province of China
City	Taipei
Period	10/1/18 → 10/1/21

UN SDG

この成果は、次の持続可能な開発目標に貢献しています

SDG 7 エネルギーをみんなに　そしてクリーンに

ASJC Scopus subject areas

コンピュータサイエンスの応用
コンピュータグラフィックスおよびコンピュータ支援設計
電子工学および電気工学

文献へのアクセス

10.1109/ASPDAC.2010.5419867

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引用スタイル

Takashima, R, Hanai, Y, Hori, Y & Kuroda, T 2010, A versatile recognition processor for sensor network applications. in 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010., 5419867, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 349-350, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, Province of China, 10/1/18. https://doi.org/10.1109/ASPDAC.2010.5419867

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abstract = "A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.",

author = "Risako Takashima and Yuya Hanai and Yuichi Hori and Tadahiro Kuroda",

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ER -

A versatile recognition processor for sensor network applications

抄録

出版物シリーズ

Other

UN SDG

ASJC Scopus subject areas

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