TY - GEN
T1 - An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator
AU - Yoshioka, Kentaro
AU - Shikata, Akira
AU - Sekimoto, Ryota
AU - Kuroda, Tadahiro
AU - Ishikuro, Hiroki
PY - 2012/12/14
Y1 - 2012/12/14
N2 - An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.
AB - An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.
UR - http://www.scopus.com/inward/record.url?scp=84870768440&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84870768440&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2012.6341365
DO - 10.1109/ESSCIRC.2012.6341365
M3 - Conference contribution
AN - SCOPUS:84870768440
SN - 9781467322126
T3 - European Solid-State Circuits Conference
SP - 381
EP - 384
BT - 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
T2 - 38th European Solid State Circuits Conference, ESSCIRC 2012
Y2 - 17 September 2012 through 21 September 2012
ER -