An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

Yohei Hasegawa; Shohei Abe; Hiroki Matsutani; Hideharu Amano; Kenichiro Anjo; Toru Awashima

doi:10.1109/FPT.2005.1568541

An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima

情報工学科

研究成果: Conference contribution

18 被引用数 (Scopus)

抄録

We propose a cryptographic accelerator for IPsec by using the NEC electronics' Dynamically Reconfigurable Processor (DRP). In our system, an embedded processor and DRP are integrated in a System-on-a-Chip (SoC) and multiple cryptographic tasks can be accelerated by DRP. Moreover, the virtual hardware mechanism, which dynamically changes its configuration data set, is introduced to realize more tasks on DRP. The evaluation results show that the throughput of each implemented cryptographic task outperformed a MIPS compatible embedded processor from 1.6 times to 7.8 times. In addition, it is shown that 80.7% of the run-time configuration overhead can be reduced by background configuration based on the double buffering method.

本文言語	English
ホスト出版物のタイトル	Proceedings - 2005 IEEE International Conference on Field Programmable Technology
ページ	163-170
ページ数	8
DOI	https://doi.org/10.1109/FPT.2005.1568541
出版ステータス	Published - 2005
イベント	2005 IEEE International Conference on Field Programmable Technology - , Singapore 継続期間: 2005 12月 11 → 2005 12月 14

出版物シリーズ

名前	Proceedings - 2005 IEEE International Conference on Field Programmable Technology
巻	2005

Other

Other	2005 IEEE International Conference on Field Programmable Technology
国/地域	Singapore
Period	05/12/11 → 05/12/14

ASJC Scopus subject areas

工学（全般）
ハードウェアとアーキテクチャ
ソフトウェア

文献へのアクセス

10.1109/FPT.2005.1568541

他のファイルとリンク

引用スタイル

Hasegawa, Y., Abe, S., Matsutani, H., Amano, H., Anjo, K., & Awashima, T. (2005). An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor. In Proceedings - 2005 IEEE International Conference on Field Programmable Technology (pp. 163-170). 記事 1568541 (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; Vol. 2005). https://doi.org/10.1109/FPT.2005.1568541

An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor. / Hasegawa, Yohei; Abe, Shohei; Matsutani, Hiroki その他.
Proceedings - 2005 IEEE International Conference on Field Programmable Technology. 2005. p. 163-170 1568541 (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; Vol. 2005).

研究成果: Conference contribution

Hasegawa, Y, Abe, S, Matsutani, H , Amano, H, Anjo, K & Awashima, T 2005, An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor. in Proceedings - 2005 IEEE International Conference on Field Programmable Technology., 1568541, Proceedings - 2005 IEEE International Conference on Field Programmable Technology, vol. 2005, pp. 163-170, 2005 IEEE International Conference on Field Programmable Technology, Singapore, 05/12/11. https://doi.org/10.1109/FPT.2005.1568541

Hasegawa Y, Abe S, Matsutani H , Amano H, Anjo K, Awashima T. An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor. In Proceedings - 2005 IEEE International Conference on Field Programmable Technology. 2005. p. 163-170. 1568541. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology). doi: 10.1109/FPT.2005.1568541

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An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

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