An FPGA implementation of reconfigurable real-time vision architecture

Jorge Hiraiwa, Hideharu Amano

研究成果: Conference contribution

15 被引用数 (Scopus)

抄録

A video processing architecture based on FPGA for real-time embedded vision systems is proposed in this paper. Recently, embedded vision systems are used in various applications. On the other hand, the throughput required to the system has been increasing as the high-definition vision replaces the current vision systems. Since more complex vision algorithms become available, higher performance and better expandability are requested accordingly. As a solution for this challenging situation, FPGA is now drawing more attention as an embedded vision system platform. In addition, high-level synthesis design is preferred instead of traditional low-level design based on hardware description languages with lower productivity. In this study, we implemented a video processing pipelined architecture which can offer flexibility for interchange processing modules. Each module was implemented using Verilog HDL and Vivado HLS for its evaluation.

本文言語English
ホスト出版物のタイトルProceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013
ページ150-155
ページ数6
DOI
出版ステータスPublished - 2013
イベント27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013 - Barcelona, Spain
継続期間: 2013 3月 252013 3月 28

出版物シリーズ

名前Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013

Other

Other27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013
国/地域Spain
CityBarcelona
Period13/3/2513/3/28

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • コンピュータ サイエンスの応用

フィンガープリント

「An FPGA implementation of reconfigurable real-time vision architecture」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル