TY - GEN
T1 - An trace-driven performance prediction method for exploring noc design optimization
AU - Niwa, Naoya
AU - Totoki, Tomohiro
AU - Matsutani, Hiroki
AU - Koibuchi, Michihiro
AU - Amano, Hideharu
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by JSPS KAKENHI Grant Number JP16670626 and #16H02816.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/12/26
Y1 - 2018/12/26
N2 - The performance prediction for a NoC-based Chip Multi-Processor (CMP) is one of the main design concerns. Generally, there is a trade-off between accuracy and time overhead on the performance prediction of computer systems. In particular, the time overhead is proportional or exponential to the number of cores when using a cycle-accurate full-system simulation, such as gem5. In this study, we propose an accurate and scalable method to predict the influence of design NoC parameters on its performance. Our method counts the number of execution cycles when employing the target NoC based on the statistics of one-time execution of a full-system simulation using a fully-connected NoC. To evaluate the accuracy and execution time overhead, we use the case that randomly generates allocations of processors with 3D mesh topology NoC. Its Mean Absolute Percentage Error of the estimated cycles is about 4.7%, and the Maximum Absolute Percentage Error is about 8.5%.
AB - The performance prediction for a NoC-based Chip Multi-Processor (CMP) is one of the main design concerns. Generally, there is a trade-off between accuracy and time overhead on the performance prediction of computer systems. In particular, the time overhead is proportional or exponential to the number of cores when using a cycle-accurate full-system simulation, such as gem5. In this study, we propose an accurate and scalable method to predict the influence of design NoC parameters on its performance. Our method counts the number of execution cycles when employing the target NoC based on the statistics of one-time execution of a full-system simulation using a fully-connected NoC. To evaluate the accuracy and execution time overhead, we use the case that randomly generates allocations of processors with 3D mesh topology NoC. Its Mean Absolute Percentage Error of the estimated cycles is about 4.7%, and the Maximum Absolute Percentage Error is about 8.5%.
KW - Network-on-Chip
KW - Optimization
KW - Performance prediction
UR - http://www.scopus.com/inward/record.url?scp=85061448351&partnerID=8YFLogxK
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U2 - 10.1109/CANDARW.2018.00042
DO - 10.1109/CANDARW.2018.00042
M3 - Conference contribution
AN - SCOPUS:85061448351
T3 - Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018
SP - 182
EP - 185
BT - Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Symposium on Computing and Networking Workshops, CANDARW 2018
Y2 - 27 November 2018 through 30 November 2018
ER -