Cache coherency protocol for multiprocessor chip

Takuya Terasawa, Satoshi Ogura, Keisuke Inoue, Hideharu Amano

研究成果: Conference article査読

5 被引用数 (Scopus)


A snoop cache protocol is proposed for the WSI implementation which minimizes the access to the shared memory. In modified-Keio protocol, both write-invalidate and write-update type protocols can be used according to the nature of the shared data. It also supports the simple synchronization mechanism with Fetch&Dec operation and inter-processor interrupt. Detailed simulation with practical parallel applications demonstrates the efficiency of this proposed protocol.

ジャーナルProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
出版ステータスPublished - 1995 1月 1
イベントProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
継続期間: 1995 1月 181995 1月 20

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 凝縮系物理学


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