抄録
This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self-aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO = 1 and CL = 0.55-pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied.
本文言語 | English |
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ページ(範囲) | 819-827 |
ページ数 | 9 |
ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | 31 |
号 | 6 |
DOI | |
出版ステータス | Published - 1996 6月 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学