Design of resource sharing reconfigurable ΔΣ SAR-ADC

Motomi Ishizuka; Kohei Yamada; Hiroki Ishikuro

doi:10.1109/ASPDAC.2018.8297338

Design of resource sharing reconfigurable ΔΣ SAR-ADC

Motomi Ishizuka, Kohei Yamada, Hiroki Ishikuro

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

This paper presents an ADC with re-configurability between SAR-only mode and delta-sigma (ΔΣ assisted mode). The ΔΣ assisted mode brings resolution enhancement. Proposed ADC shares a capacitor array for SAR, feedback DAC, and integrator capacitor in ΔΣ loop, which can reduce the circuit size. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at 32 MS/s and power consumption of 0.55 mW. The SNDR is improved to 62.9 dB by ΔΣ assisted mode.

本文言語	English
ホスト出版物のタイトル	ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	317-318
ページ数	2
巻	2018-January
ISBN（電子版）	9781509006021
DOI	https://doi.org/10.1109/ASPDAC.2018.8297338
出版ステータス	Published - 2018 2月 20
イベント	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of 継続期間: 2018 1月 22 → 2018 1月 25

Other

Other	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
国/地域	Korea, Republic of
City	Jeju
Period	18/1/22 → 18/1/25

ASJC Scopus subject areas

電子工学および電気工学
コンピュータサイエンスの応用
コンピュータグラフィックスおよびコンピュータ支援設計

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10.1109/ASPDAC.2018.8297338

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引用スタイル

Ishizuka, M, Yamada, K & Ishikuro, H 2018, Design of resource sharing reconfigurable ΔΣ SAR-ADC. in ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 317-318, 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea, Republic of, 18/1/22. https://doi.org/10.1109/ASPDAC.2018.8297338

@inproceedings{da2e72136ad747d7895552685fabdd14,

title = "Design of resource sharing reconfigurable ΔΣ SAR-ADC",

abstract = "This paper presents an ADC with re-configurability between SAR-only mode and delta-sigma (ΔΣ assisted mode). The ΔΣ assisted mode brings resolution enhancement. Proposed ADC shares a capacitor array for SAR, feedback DAC, and integrator capacitor in ΔΣ loop, which can reduce the circuit size. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at 32 MS/s and power consumption of 0.55 mW. The SNDR is improved to 62.9 dB by ΔΣ assisted mode.",

author = "Motomi Ishizuka and Kohei Yamada and Hiroki Ishikuro",

year = "2018",

month = feb,

day = "20",

doi = "10.1109/ASPDAC.2018.8297338",

language = "English",

volume = "2018-January",

pages = "317--318",

booktitle = "ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 ; Conference date: 22-01-2018 Through 25-01-2018",

}

TY - GEN

T1 - Design of resource sharing reconfigurable ΔΣ SAR-ADC

AU - Ishizuka, Motomi

AU - Yamada, Kohei

AU - Ishikuro, Hiroki

PY - 2018/2/20

Y1 - 2018/2/20

N2 - This paper presents an ADC with re-configurability between SAR-only mode and delta-sigma (ΔΣ assisted mode). The ΔΣ assisted mode brings resolution enhancement. Proposed ADC shares a capacitor array for SAR, feedback DAC, and integrator capacitor in ΔΣ loop, which can reduce the circuit size. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at 32 MS/s and power consumption of 0.55 mW. The SNDR is improved to 62.9 dB by ΔΣ assisted mode.

AB - This paper presents an ADC with re-configurability between SAR-only mode and delta-sigma (ΔΣ assisted mode). The ΔΣ assisted mode brings resolution enhancement. Proposed ADC shares a capacitor array for SAR, feedback DAC, and integrator capacitor in ΔΣ loop, which can reduce the circuit size. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at 32 MS/s and power consumption of 0.55 mW. The SNDR is improved to 62.9 dB by ΔΣ assisted mode.

UR - http://www.scopus.com/inward/record.url?scp=85045336486&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85045336486&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2018.8297338

DO - 10.1109/ASPDAC.2018.8297338

M3 - Conference contribution

AN - SCOPUS:85045336486

VL - 2018-January

SP - 317

EP - 318

BT - ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018

Y2 - 22 January 2018 through 25 January 2018

ER -

Design of resource sharing reconfigurable ΔΣ SAR-ADC

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