抄録
This paper proposes a Digital Signal Processing (DSP) type Phase Synchronizer with the Method of Least Squares (PS-MLS). Its construction is quite different from that of the conventional Phase-locked loop (PLL);there are not loop filter nor voltage controlled oscillator (VCO) in the PS-MLS. The behavior of the PS-MLS is unique. First, the input phase component is calculated. Then the input phase component is linearized and noise component is greatly reduced by modified Method of Least Squares. The proposed PS-MLS can satisfy three requirements on PLL; fast acquisition, wide pull-in range, and good noise suppression, simultaneously. The superior performances of the PS-MLS are confirmed by computer simulations.
本文言語 | English |
---|---|
ページ(範囲) | 814-819 |
ページ数 | 6 |
ジャーナル | IEEE Transactions on Consumer Electronics |
巻 | 35 |
号 | 4 |
DOI | |
出版ステータス | Published - 1989 |
ASJC Scopus subject areas
- メディア記述
- 電子工学および電気工学