@inproceedings{9df6943b111e4564adb0f67e74efc59b,
title = "Dynamic instruction cascading on GALS microprocessors",
abstract = "As difficulty and the costs of distributing a single global clock throughout a processor is growing generation by generation, GloballyAsynchronous Locally-Synchronous (GALS) designs are an alternative approach to the conventional synchronous processors. In this paper, we propose Dynamic Instruction Cascading (DIG). DIG is a technique to execute two dependent instructions in one cycle by scaling down the clock frequency. Lowering the clock frequency enables the signal to reach farther, thereby computing two instructions in one cycle becomes possible. DIG is effectively applied to GALS processors because lowering only the clock frequency of the target domain is needed and therefore unwanted performance degradation will be prevented. The results showed average performance improvement of 7% on SPEC CPU2000 Integer and MediaBench applications when assuming that DIG is possible by lowering the clock frequency to 80%.",
author = "Hiroshi Sasaki and Masaaki Kondo and Hiroshi Nakamura",
year = "2005",
doi = "10.1007/11556930_4",
language = "English",
isbn = "3540290133",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "30--39",
booktitle = "Integrated Circuit and System Design",
note = "15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005 ; Conference date: 20-09-2005 Through 23-09-2005",
}