EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET.

K. Matsumoto; N. Hashizume; N. Atoda; Y. Awano

EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET.

K. Matsumoto
, N. Hashizume
, N. Atoda
, Y. Awano

研究成果: Conference contribution

抄録

The substrate current under the channel layer in a sub-micron gate self-aligned GaAs FET is shown by Monte Carlo simulation to be the major cause of the short channel effects. By introducing a p-type layer between the channel layer and the substrate, the short channel effects of the FETs having sub-micron gate length are suppressed significantly.

本文言語	English
ホスト出版物のタイトル	Institute of Physics Conference Series
編集者	B. de Cremoux
ページ	515-520
ページ数	6
版	74
出版ステータス	Published - 1985 12月 1
外部発表	はい

出版物シリーズ

名前	Institute of Physics Conference Series
番号	74
ISSN（印刷版）	0373-0751

ASJC Scopus subject areas

物理学および天文学一般

他のファイルとリンク

引用スタイル

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abstract = "The substrate current under the channel layer in a sub-micron gate self-aligned GaAs FET is shown by Monte Carlo simulation to be the major cause of the short channel effects. By introducing a p-type layer between the channel layer and the substrate, the short channel effects of the FETs having sub-micron gate length are suppressed significantly.",

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AU - Atoda, N.

AU - Awano, Y.

PY - 1985/12/1

Y1 - 1985/12/1

N2 - The substrate current under the channel layer in a sub-micron gate self-aligned GaAs FET is shown by Monte Carlo simulation to be the major cause of the short channel effects. By introducing a p-type layer between the channel layer and the substrate, the short channel effects of the FETs having sub-micron gate length are suppressed significantly.

AB - The substrate current under the channel layer in a sub-micron gate self-aligned GaAs FET is shown by Monte Carlo simulation to be the major cause of the short channel effects. By introducing a p-type layer between the channel layer and the substrate, the short channel effects of the FETs having sub-micron gate length are suppressed significantly.

UR - https://www.scopus.com/pages/publications/0022187518

UR - https://www.scopus.com/pages/publications/0022187518#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:0022187518

SN - 0854981659

T3 - Institute of Physics Conference Series

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EP - 520

BT - Institute of Physics Conference Series

A2 - de Cremoux, B.

ER -

EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET.

抄録

出版物シリーズ

ASJC Scopus subject areas

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