TY - GEN
T1 - Fabrication and characterization of Si/SiGe quantum dots with capping gate
AU - Kodera, Tetsuo
AU - Fukuoka, Yuji
AU - Takeda, Kenta
AU - Obata, Toshiaki
AU - Yoshida, Katsuharu
AU - Sawano, Kentaro
AU - Uchida, Ken
AU - Shiraki, Yasuhiro
AU - Tarucha, Seigo
AU - Oda, Shunri
PY - 2012
Y1 - 2012
N2 - We study transport properties of quantum point contacts (QPCs) and quantum dots (QDs) with a global capping gate, fabricated on a Si/SiGe high electron mobility transistor (HEMT) wafer. By biasing the capping gate negatively, we succeed in making QPC operation point of surface Schottky gate negatively smaller and then reducing noise. We also observe Coulomb oscillations using a QD structure by suppressing charging noise with negative capping gate voltage.
AB - We study transport properties of quantum point contacts (QPCs) and quantum dots (QDs) with a global capping gate, fabricated on a Si/SiGe high electron mobility transistor (HEMT) wafer. By biasing the capping gate negatively, we succeed in making QPC operation point of surface Schottky gate negatively smaller and then reducing noise. We also observe Coulomb oscillations using a QD structure by suppressing charging noise with negative capping gate voltage.
UR - http://www.scopus.com/inward/record.url?scp=84867211370&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84867211370&partnerID=8YFLogxK
U2 - 10.1109/SNW.2012.6243291
DO - 10.1109/SNW.2012.6243291
M3 - Conference contribution
AN - SCOPUS:84867211370
SN - 9781467309943
T3 - 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012
BT - 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012
T2 - 2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012
Y2 - 10 June 2012 through 11 June 2012
ER -