TY - GEN
T1 - FPL Demo
T2 - 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022
AU - Kuga, Morihiro
AU - Iida, Masahiro
AU - Amano, Hideharu
N1 - Funding Information:
IV. DEMONSTRATION We will demonstrate the real prototype chip working for several applications, and its design tools. This work was supported by JST CREST Grant Number JPMJCR19K1.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This demonstration shows a prototype chip of SLM (Scalable Logic Module) for a novel FPGA-IP embedded in various chips for edge computing. In this paper, the authors briefly describe the architecture of our FPGA-IP and the evaluation environment for the prototype chip.
AB - This demonstration shows a prototype chip of SLM (Scalable Logic Module) for a novel FPGA-IP embedded in various chips for edge computing. In this paper, the authors briefly describe the architecture of our FPGA-IP and the evaluation environment for the prototype chip.
KW - FPGA
KW - IoT
KW - Multi-access Edge Computing
UR - http://www.scopus.com/inward/record.url?scp=85149288855&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85149288855&partnerID=8YFLogxK
U2 - 10.1109/FPL57034.2022.00083
DO - 10.1109/FPL57034.2022.00083
M3 - Conference contribution
AN - SCOPUS:85149288855
T3 - Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022
SP - 467
BT - Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 29 August 2022 through 2 September 2022
ER -