TY - GEN
T1 - Hardware support for MPI in DIMMnet-2 network interface
AU - Tanabe, Noboru
AU - Kitamura, Akira
AU - Miyashiro, Tomotaka
AU - Miyabe, Yasuo
AU - Araki, Takeshi
AU - Luo, Zhengzhe
AU - Nakajo, Hironori
AU - Amano, Hideharu
PY - 2006
Y1 - 2006
N2 - In this paper, hardware support for MPI on the DIMMnet-2 network interface plugged into a DDR DIMM slot is presented. This hardware support realize effective eager protocol and effective derived datatype communication of MPI. As a preliminary evaluation, the evaluation results on the real prototype concerning the bandwidth of elements constituting MPI are shown. IPUSH, which is remote indirect writing, showed almost the same performance as RDMA, which is remote direct writing. IPUSH can reduce memory space required for a receiver buffer sharply The memory space reduction effect of IPUSH on a system with more nodes is higher. Compared with a method that starts the burst vector loading many times, VLS, which performs a regular-interval vector loading, sharply accelerated access to the data arranged at regular intervals. The above-mentioned results indicate that the improvement in the speed of MPI by the proposed method is promising.
AB - In this paper, hardware support for MPI on the DIMMnet-2 network interface plugged into a DDR DIMM slot is presented. This hardware support realize effective eager protocol and effective derived datatype communication of MPI. As a preliminary evaluation, the evaluation results on the real prototype concerning the bandwidth of elements constituting MPI are shown. IPUSH, which is remote indirect writing, showed almost the same performance as RDMA, which is remote direct writing. IPUSH can reduce memory space required for a receiver buffer sharply The memory space reduction effect of IPUSH on a system with more nodes is higher. Compared with a method that starts the burst vector loading many times, VLS, which performs a regular-interval vector loading, sharply accelerated access to the data arranged at regular intervals. The above-mentioned results indicate that the improvement in the speed of MPI by the proposed method is promising.
UR - http://www.scopus.com/inward/record.url?scp=46449115526&partnerID=8YFLogxK
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U2 - 10.1109/IWIAS.2006.26
DO - 10.1109/IWIAS.2006.26
M3 - Conference contribution
AN - SCOPUS:46449115526
SN - 0769526896
SN - 9780769526898
T3 - Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
SP - 73
EP - 80
BT - Proceedings - International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006
T2 - International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006
Y2 - 23 January 2006 through 25 January 2006
ER -