Hardware/software co-design architecture for Blokus Duo solver

Naru Sugimoto, Hideharu Amano

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

This paper presents a software and hardware design of an FPGA-based Blokus Duo solver. We used Embedded system called ZYNQ-7000 All Programmable SoC to implement the solver. By combining hardware with software, efficient acceleration is performed. Our system searches a game tree by using the miniMax algorithm with alpha-beta pruning. The implemented solver works at 75MHz with Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 on the Digilent ZedBoard. It can search states after three moves in most cases.

本文言語English
ホスト出版物のタイトルProceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ページ358-361
ページ数4
ISBN(電子版)9781479962457
DOI
出版ステータスPublished - 2014
イベント13th International Conference on Field-Programmable Technology, FPT 2014 - Shanghai, China
継続期間: 2014 12月 102014 12月 12

Other

Other13th International Conference on Field-Programmable Technology, FPT 2014
国/地域China
CityShanghai
Period14/12/1014/12/12

ASJC Scopus subject areas

  • 計算理論と計算数学
  • コンピュータ サイエンスの応用

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