TY - GEN
T1 - High-Bandwidth Low-Latency Approximate Interconnection Networks
AU - Fujiki, Daichi
AU - Ishii, Kiyo
AU - Fujiwara, Ikki
AU - Matsutani, Hiroki
AU - Amano, Hideharu
AU - Casanova, Henri
AU - Koibuchi, Michihiro
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/5/5
Y1 - 2017/5/5
N2 - Computational applications are subject to various kinds of numerical errors, ranging from deterministic round-off errors to soft errors caused by non-deterministic bit flips, which do not lead to application failure but corrupt application results. Non-deterministic bit flips are typically mitigated in hardware using various error correcting codes (ECC). But in practice, due to performance and cost concerns, these techniques do not guarantee error-free execution. On large-scale computing platforms, soft errors occur with non-negligible probability in RAM and on the CPU, and it has become clear that applications must tolerate them. For some applications, this tolerance is intrinsic as result quality can remain acceptable even in the presence of soft errors (e.g., data analysis applications, multimedia applications). Tolerance can also be built into the application, resolving data corruptions in software during application execution. By contrast, today's optical networks hold on to a rigid error-free standard, which imposes limits on network performance scalability. In this work we propose high-bandwidth, low-latency approximate networks with the following three features:(1) Optical links that exploit multi-level quadrature amplitude modulation (QAM) for achieving high bandwidth, (2) Avoidance of forward error correction (FEC), which makes optical link error-prone but affords lower latency, and(3) The use of symbol mapping coding between bit sequence and QAM to ensure data integrity that is sufficient for practical soft-error-tolerant applications. Discrete-event simulation results for application benchmarks show that approx networks achieve speedups up to 2.94 when compared to conventional networks.
AB - Computational applications are subject to various kinds of numerical errors, ranging from deterministic round-off errors to soft errors caused by non-deterministic bit flips, which do not lead to application failure but corrupt application results. Non-deterministic bit flips are typically mitigated in hardware using various error correcting codes (ECC). But in practice, due to performance and cost concerns, these techniques do not guarantee error-free execution. On large-scale computing platforms, soft errors occur with non-negligible probability in RAM and on the CPU, and it has become clear that applications must tolerate them. For some applications, this tolerance is intrinsic as result quality can remain acceptable even in the presence of soft errors (e.g., data analysis applications, multimedia applications). Tolerance can also be built into the application, resolving data corruptions in software during application execution. By contrast, today's optical networks hold on to a rigid error-free standard, which imposes limits on network performance scalability. In this work we propose high-bandwidth, low-latency approximate networks with the following three features:(1) Optical links that exploit multi-level quadrature amplitude modulation (QAM) for achieving high bandwidth, (2) Avoidance of forward error correction (FEC), which makes optical link error-prone but affords lower latency, and(3) The use of symbol mapping coding between bit sequence and QAM to ensure data integrity that is sufficient for practical soft-error-tolerant applications. Discrete-event simulation results for application benchmarks show that approx networks achieve speedups up to 2.94 when compared to conventional networks.
KW - Approximate computing
KW - Interconnect and network interface architectures
UR - http://www.scopus.com/inward/record.url?scp=85019605853&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85019605853&partnerID=8YFLogxK
U2 - 10.1109/HPCA.2017.38
DO - 10.1109/HPCA.2017.38
M3 - Conference contribution
AN - SCOPUS:85019605853
T3 - Proceedings - International Symposium on High-Performance Computer Architecture
SP - 469
EP - 480
BT - Proceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017
PB - IEEE Computer Society
T2 - 23rd IEEE Symposium on High Performance Computer Architecture, HPCA 2017
Y2 - 4 February 2017 through 8 February 2017
ER -