HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

S. Notomi; Y. Awano; M. Kosugi; T. Nagata; K. Kosemura; M. Ono; N. Kobayashi; H. Ishiwari; K. Odani; T. Mimura; M. Abe

HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

S. Notomi, Y. Awano, M. Kosugi, T. Nagata, K. Kosemura, M. Ono, N. Kobayashi, H. Ishiwari, K. Odani, T. Mimura, M. Abe

研究成果: Paper › 査読

抄録

A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.

本文言語	English
ページ	177-180
ページ数	4
出版ステータス	Published - 1987
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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引用スタイル

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title = "HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.",

abstract = "A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.",

author = "S. Notomi and Y. Awano and M. Kosugi and T. Nagata and K. Kosemura and M. Ono and N. Kobayashi and H. Ishiwari and K. Odani and T. Mimura and M. Abe",

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TY - CONF

T1 - HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

AU - Notomi, S.

AU - Awano, Y.

AU - Kosugi, M.

AU - Nagata, T.

AU - Kosemura, K.

AU - Ono, M.

AU - Kobayashi, N.

AU - Ishiwari, H.

AU - Odani, K.

AU - Mimura, T.

AU - Abe, M.

PY - 1987

Y1 - 1987

N2 - A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.

AB - A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.

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M3 - Paper

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ER -

HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

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ASJC Scopus subject areas

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