This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1 Gbit/s.
|ジャーナル||IEICE Transactions on Communications|
|出版ステータス||Published - 1993 3月 1|
ASJC Scopus subject areas
- コンピュータ ネットワークおよび通信