TY - JOUR
T1 - IMPLEMENTATION OF A NEW TYPE DSP PLL USING HIGH PERFORMANCE DSP DSSP-1.
AU - Ono, S.
AU - Aoyama, T.
AU - Hagiwara, M.
AU - Nakagawa, M.
PY - 1986/12/1
Y1 - 1986/12/1
N2 - The authors describe a new digital processing phase lock loop (PLL) implemented on the DSSP 1 high-performance digital signal processor. The new PLL has linear phase comparison characteristics and is called the linear digital PLL. It exhibits fast acquisition without an increase in jitter, its pull-in range is wider, and its steady-state errors and sampling frequency are lower than those of conventional PLLs. It also does not require automatic gain control.
AB - The authors describe a new digital processing phase lock loop (PLL) implemented on the DSSP 1 high-performance digital signal processor. The new PLL has linear phase comparison characteristics and is called the linear digital PLL. It exhibits fast acquisition without an increase in jitter, its pull-in range is wider, and its steady-state errors and sampling frequency are lower than those of conventional PLLs. It also does not require automatic gain control.
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M3 - Conference article
AN - SCOPUS:0022920128
SN - 0736-7791
SP - 2195
EP - 2198
JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
JF - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
ER -