TY - JOUR
T1 - Implementation of super high definition image processing on HiPIPE
AU - Fujii, Tetsurou
AU - Sawabe, Tomoko
AU - Ohta, Naohisa
AU - Ono, Sadayasu
PY - 1991/12/1
Y1 - 1991/12/1
N2 - In order to manipulate SHD (super high definition) images, a novel parallel processing unit called HiPIPE (Highly Parallel Image Processing Engine) is developed as a project of NOVI-II. The engine is connected to an SHD image display unit and an image data storage unit. Extremely high computational power is obtained by a multicomputer type parallel processing technique. 128 processing elements are connected by a mesh network. Various image coding schemes are carefully explored from the viewpoint of parallel processing, and the problem of processor connections is examined. A novel load-balancing technique, called 2-dimensional butterfly data shuffling, is developed and implemented. The current version of HiPIPE uses just 128 scaler processing elements and has more than twice the power of a single-processor CRAY-2 for a still SHD image coding task.
AB - In order to manipulate SHD (super high definition) images, a novel parallel processing unit called HiPIPE (Highly Parallel Image Processing Engine) is developed as a project of NOVI-II. The engine is connected to an SHD image display unit and an image data storage unit. Extremely high computational power is obtained by a multicomputer type parallel processing technique. 128 processing elements are connected by a mesh network. Various image coding schemes are carefully explored from the viewpoint of parallel processing, and the problem of processor connections is examined. A novel load-balancing technique, called 2-dimensional butterfly data shuffling, is developed and implemented. The current version of HiPIPE uses just 128 scaler processing elements and has more than twice the power of a single-processor CRAY-2 for a still SHD image coding task.
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M3 - Conference article
AN - SCOPUS:0026391776
SN - 0271-4310
VL - 1
SP - 348
EP - 351
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - 1991 IEEE International Symposium on Circuits and Systems Part 1 (of 5)
Y2 - 11 June 1991 through 14 June 1991
ER -