Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link

Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda

研究成果: Conference contribution

27 被引用数 (Scopus)

抄録

This paper discusses interference of an inductive-coupling link in 65nm CMOS. Electromagnetic interference from power/signal lines and to SRAM was simulated and measured. Interference from power lines for mobile applications (line and space) is smaller than that for high-performance applications (mesh type). Interference from signal lines requires only 9% of additional transmit power even in the worst case of logic circuits. In typical operation range, interference to SRAM is ignorable. Only when supply voltage is much lower than typical range, the bit-line noise from the inductive-coupling link influences SRAM operation. Interference to SRAM is small compared with other influences such as device variations and soft errors.

本文言語English
ホスト出版物のタイトル2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
ページ131-134
ページ数4
DOI
出版ステータスPublished - 2007
イベント2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of
継続期間: 2007 11月 122007 11月 14

出版物シリーズ

名前2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
国/地域Korea, Republic of
CityJeju
Period07/11/1207/11/14

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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