TY - JOUR
T1 - Layered I/O architecture in a multicomputer type DSP system for video communications
AU - Sakurai, Naoya
AU - Fujii, Tetsurou
AU - Ohta, Naohisa
PY - 1989/12/1
Y1 - 1989/12/1
N2 - A layered I/O architecture in a multicomputer-type DSP system is described that achieves efficient load balancing and high-speed video data distribution/gathering for real-time video processing. The layered structure is based on global distribution using buses and local distribution serial links. In addition to multiple homogeneous processing elements, the concept of bus nodes with high data distribution rates is introduced. System performance is evaluated by computer simulation focusing on load balancing efficiency using a typical video processing algorithm. It is shown that load balancing, which combines task assignment control with large-grain data flow, can provide high performance.
AB - A layered I/O architecture in a multicomputer-type DSP system is described that achieves efficient load balancing and high-speed video data distribution/gathering for real-time video processing. The layered structure is based on global distribution using buses and local distribution serial links. In addition to multiple homogeneous processing elements, the concept of bus nodes with high data distribution rates is introduced. System performance is evaluated by computer simulation focusing on load balancing efficiency using a typical video processing algorithm. It is shown that load balancing, which combines task assignment control with large-grain data flow, can provide high performance.
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M3 - Conference article
AN - SCOPUS:0024906903
SN - 0271-4310
VL - 1
SP - 242
EP - 245
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - IEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1
Y2 - 8 May 1989 through 11 May 1989
ER -