Level-shifter-less approach for multi-V                         DD                          design to use body bias control in FD-SOI

Kimiyoshi Usami; Shunsuke Kogure; Yusuke Yoshida; Ryo Magasaki; Hideharu Amano

doi:10.1109/VLSI-SoC.2017.8203473

Level-shifter-less approach for multi-V _DD design to use body bias control in FD-SOI

Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano

情報工学科

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip demonstrated that the chip applying the LSL approach correctly operates at VDDL=0.6V and VDDH=1.2V under RBB of 2V for pMOS transistors while suppressing the static dc current in the VDDH domain.

本文言語	English
ホスト出版物のタイトル	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
出版社	IEEE Computer Society
ISBN（電子版）	9781538628805
DOI	https://doi.org/10.1109/VLSI-SoC.2017.8203473
出版ステータス	Published - 2017 12月 13
イベント	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates 継続期間: 2017 10月 23 → 2017 10月 25

出版物シリーズ

名前	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN（印刷版）	2324-8432
ISSN（電子版）	2324-8440

Other

Other	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
国/地域	United Arab Emirates
City	Abu Dhabi
Period	17/10/23 → 17/10/25

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
ソフトウェア
電子工学および電気工学

文献へのアクセス

10.1109/VLSI-SoC.2017.8203473

他のファイルとリンク

引用スタイル

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R., & Amano, H. (2017). Level-shifter-less approach for multi-V _DD design to use body bias control in FD-SOI In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings Article 8203473 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2017.8203473

Level-shifter-less approach for multi-V _DD design to use body bias control in FD-SOI . / Usami, Kimiyoshi; Kogure, Shunsuke; Yoshida, Yusuke その他.
25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 2017. 8203473 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

研究成果: Conference contribution

Usami, K, Kogure, S, Yoshida, Y, Magasaki, R & Amano, H 2017, Level-shifter-less approach for multi-V _DD design to use body bias control in FD-SOI in 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings., 8203473, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, 17/10/23. https://doi.org/10.1109/VLSI-SoC.2017.8203473

Usami K, Kogure S, Yoshida Y, Magasaki R, Amano H. Level-shifter-less approach for multi-V _DD design to use body bias control in FD-SOI In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society. 2017. 8203473. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC.2017.8203473

Usami, Kimiyoshi ; Kogure, Shunsuke ; Yoshida, Yusuke その他. / Level-shifter-less approach for multi-V _DD design to use body bias control in FD-SOI 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 2017. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

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abstract = "Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip demonstrated that the chip applying the LSL approach correctly operates at VDDL=0.6V and VDDH=1.2V under RBB of 2V for pMOS transistors while suppressing the static dc current in the VDDH domain.",

keywords = "Body bias control, FD-SOI, Level shifter, Low power, Multi-VDD design",

author = "Kimiyoshi Usami and Shunsuke Kogure and Yusuke Yoshida and Ryo Magasaki and Hideharu Amano",

note = "Funding Information: ACKNOWLEDGMENT This work was partially supported by JSPS KAKENHI S Grant Number 25220002. This work was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc. This presentation was supported by SIT Research Center for Green Innovation. Publisher Copyright: {\textcopyright} 2017 IEEE.; 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 ; Conference date: 23-10-2017 Through 25-10-2017",

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AU - Magasaki, Ryo

AU - Amano, Hideharu

N1 - Funding Information: ACKNOWLEDGMENT This work was partially supported by JSPS KAKENHI S Grant Number 25220002. This work was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc. This presentation was supported by SIT Research Center for Green Innovation. Publisher Copyright: © 2017 IEEE.

PY - 2017/12/13

Y1 - 2017/12/13

N2 - Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip demonstrated that the chip applying the LSL approach correctly operates at VDDL=0.6V and VDDH=1.2V under RBB of 2V for pMOS transistors while suppressing the static dc current in the VDDH domain.

AB - Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip demonstrated that the chip applying the LSL approach correctly operates at VDDL=0.6V and VDDH=1.2V under RBB of 2V for pMOS transistors while suppressing the static dc current in the VDDH domain.

KW - Body bias control

KW - FD-SOI

KW - Level shifter

KW - Low power

KW - Multi-VDD design

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Level-shifter-less approach for multi-V DD design to use body bias control in FD-SOI

抄録