Logic compatible process technology for embedded atom switches in CMOS

We have developed a CMOS logic compatible process for embedding Cu atom switches in a Cu/low-k back-end-of-line without degrading interconnect and switch performance characteristics. The key technologies are (i) burying a via-interlayer dielectric layer between the switches without voids, followed by surface planarization using chemical mechanical polishing, and (ii) introducing a Ta protective second top electrode, which realizes simultaneous via-openings to both the switches and the lower interconnects without degrading physical morphology and electric properties of the switches. The developed process enables us to integrate the atom switches on logic with only two additional masks at low cost.