TY - GEN
T1 - MCMA
T2 - 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013
AU - Chaintreuil, Remi
AU - Uno, Rie
AU - Amano, Hideharu
PY - 2013/1/1
Y1 - 2013/1/1
N2 - The Cool Mega-Array is a highly power-efficient coarse-grained reconfigurable accelerator, particularly aimed toward multimedia applications executed on battery-driven devices. It consists of a large processing elements array, without any memory element, a simple micro-controller for data management and the data memory. The power consumption of the PE array itself is very low, and can be further reduced by dynamically scaling its power voltage in order to adapt to the desired speed of computation. A modular version of this design is proposed, which provides the ability to reconfigure the PE array structure, and adapt its size to the application. This allows the execution of applications with different complexities and degrees of parallelism on a relatively smaller chip, compared to simply using a large PE array, depending on the implementation choices and the set of applications (4 times less processing elements in the implementation example). Power-leakage can also be reduced by using coarse-grained power-gating.
AB - The Cool Mega-Array is a highly power-efficient coarse-grained reconfigurable accelerator, particularly aimed toward multimedia applications executed on battery-driven devices. It consists of a large processing elements array, without any memory element, a simple micro-controller for data management and the data memory. The power consumption of the PE array itself is very low, and can be further reduced by dynamically scaling its power voltage in order to adapt to the desired speed of computation. A modular version of this design is proposed, which provides the ability to reconfigure the PE array structure, and adapt its size to the application. This allows the execution of applications with different complexities and degrees of parallelism on a relatively smaller chip, compared to simply using a large PE array, depending on the implementation choices and the set of applications (4 times less processing elements in the implementation example). Power-leakage can also be reduced by using coarse-grained power-gating.
UR - http://www.scopus.com/inward/record.url?scp=84894455703&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84894455703&partnerID=8YFLogxK
U2 - 10.1109/ReConFig.2013.6732308
DO - 10.1109/ReConFig.2013.6732308
M3 - Conference contribution
AN - SCOPUS:84894455703
SN - 9781479920792
T3 - 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013
BT - 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013
PB - IEEE Computer Society
Y2 - 9 December 2013 through 11 December 2013
ER -