TY - GEN
T1 - MuCCRA-Cube
T2 - FPL 09: 19th International Conference on Field Programmable Logic and Applications
AU - Saito, S.
AU - Kohama, Y.
AU - Sugimori, Y.
AU - Hasegawa, Y.
AU - Matsutani, H.
AU - Sano, T.
AU - Kasuga, K.
AU - Yoshida, Y.
AU - Niitsu, K.
AU - Miura, N.
AU - Kuroda, T.
AU - Amano, H.
PY - 2009/11/25
Y1 - 2009/11/25
N2 - MuCCRA-Cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90nm CMOS process consisting of four dies each of which has a 4 x 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and the average execution time is reduced to 31% compared to that using a single chip.
AB - MuCCRA-Cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90nm CMOS process consisting of four dies each of which has a 4 x 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and the average execution time is reduced to 31% compared to that using a single chip.
UR - http://www.scopus.com/inward/record.url?scp=70450092775&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70450092775&partnerID=8YFLogxK
U2 - 10.1109/FPL.2009.5272565
DO - 10.1109/FPL.2009.5272565
M3 - Conference contribution
AN - SCOPUS:70450092775
SN - 9781424438921
T3 - FPL 09: 19th International Conference on Field Programmable Logic and Applications
SP - 6
EP - 11
BT - FPL 09
Y2 - 31 August 2009 through 2 September 2009
ER -