Newly Structured Expandable 52-Mbit/s, 48-Channel Time-Division Switching LSI with 2.4 Gbit/s Throughput

N. Yamanaka; S. Kikuchi; H. Miyanaga

doi:10.1049/el:19900341

Newly Structured Expandable 52-Mbit/s, 48-Channel Time-Division Switching LSI with 2.4 Gbit/s Throughput

N. Yamanaka
, S. Kikuchi
, H. Miyanaga

研究成果: Article › 査読

4 被引用数 (Scopus)

抄録

An expandable Si bipolar 2.4Gbit/s throughput, 52Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4Gbit/s and a power-dissipation of 5-3 W are achieved by adopting a low-voltage swing fourserial-gated differential bipolar circuit design and super selfaligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems of future B-ISDN.

本文言語	English
ページ（範囲）	524-526
ページ数	3
ジャーナル	Electronics Letters
巻	26
号	8
DOI	https://doi.org/10.1049/el:19900341
出版ステータス	Published - 1990 1月 1
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1049/el:19900341

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title = "Newly Structured Expandable 52-Mbit/s, 48-Channel Time-Division Switching LSI with 2.4 Gbit/s Throughput",

abstract = "An expandable Si bipolar 2.4Gbit/s throughput, 52Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4Gbit/s and a power-dissipation of 5-3 W are achieved by adopting a low-voltage swing fourserial-gated differential bipolar circuit design and super selfaligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems of future B-ISDN.",

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AU - Miyanaga, H.

PY - 1990/1/1

Y1 - 1990/1/1

N2 - An expandable Si bipolar 2.4Gbit/s throughput, 52Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4Gbit/s and a power-dissipation of 5-3 W are achieved by adopting a low-voltage swing fourserial-gated differential bipolar circuit design and super selfaligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems of future B-ISDN.

AB - An expandable Si bipolar 2.4Gbit/s throughput, 52Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4Gbit/s and a power-dissipation of 5-3 W are achieved by adopting a low-voltage swing fourserial-gated differential bipolar circuit design and super selfaligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems of future B-ISDN.

KW - Bipolar devices

KW - Circuit theory and design

KW - Large scale integration

KW - Silicon

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Newly Structured Expandable 52-Mbit/s, 48-Channel Time-Division Switching LSI with 2.4 Gbit/s Throughput

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