This paper discusses a novel approach to realizing a flexible high speed signal transport system for the multimedia network. We propose a flexible transport system architecture based on reconfigurable hardware. The proposed architecture realizes all the functions needed for high speed telecommunication systems which include physical interfaces, programmable buffer memory, bi-directional processing, multiclock processing and co-processing using dedicated processors for higher layer processing. We develop an experimental prototype system using the custom designed reconfigurable hardware called PROTEUS. We also discuss a design methodology for achieving flexible transport systems. Experimental results for 156Mbps SDH/ATM processing circuits are shown. Our experimental results show the feasibility of achieving both flexibility and high speed processing in high speed digital transport systems.
|Published - 1995
|Proceedings of the 1995 IEEE Global Telecommunications Conference. Part 2 (of 3) - Singapore, Singapore
継続期間: 1995 11月 14 → 1995 11月 16
|Proceedings of the 1995 IEEE Global Telecommunications Conference. Part 2 (of 3)
|95/11/14 → 95/11/16
ASJC Scopus subject areas