TY - GEN
T1 - Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches
AU - Ito, Kohei
AU - Yasudo, Ryota
AU - Amano, Hideharu
N1 - Funding Information:
This work was supported by JST CREST Grant Number JPMJCR19Kl.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Multi-FPGA systems have received an attention as a computing cluster for multi-access edge computing (MEC). Also, they can process time-critical jobs with their hardwired logic. For this purpose, the static time-division multiplexing (STDM) network is adopted because it enables to predict latency and bandwidth. However, the overall performance of the STDM network depends on the number of time slots. This paper proposes a new mapping tool that optimizes the application mapping so that the number of slots is minimized. Our tool handles multicasts and multi-ejection function which are effective techniques for STDM switches implemented on an FPGA cluster. For applications with all-to-all communication, our experimental results show that the tool reduces the number of time slots by 59-68% with both multicasts and multi-ejection switches.
AB - Multi-FPGA systems have received an attention as a computing cluster for multi-access edge computing (MEC). Also, they can process time-critical jobs with their hardwired logic. For this purpose, the static time-division multiplexing (STDM) network is adopted because it enables to predict latency and bandwidth. However, the overall performance of the STDM network depends on the number of time slots. This paper proposes a new mapping tool that optimizes the application mapping so that the number of slots is minimized. Our tool handles multicasts and multi-ejection function which are effective techniques for STDM switches implemented on an FPGA cluster. For applications with all-to-all communication, our experimental results show that the tool reduces the number of time slots by 59-68% with both multicasts and multi-ejection switches.
KW - multi-ejection
KW - multi-FPGA
KW - STDM
UR - http://www.scopus.com/inward/record.url?scp=85149307809&partnerID=8YFLogxK
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U2 - 10.1109/FPL57034.2022.00032
DO - 10.1109/FPL57034.2022.00032
M3 - Conference contribution
AN - SCOPUS:85149307809
T3 - Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022
SP - 143
EP - 147
BT - Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022
Y2 - 29 August 2022 through 2 September 2022
ER -