Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Yohei Hasegawa; Shohei Abe; Shunsuke Kurotaki; Vu Manh Tuan; Naohiro Katsura; Takuro Nakamura; Takashi Nishimura; Hideharu Amano

doi:10.1109/IPDPS.2006.1639431

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano

情報工学科

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.

本文言語	English
ホスト出版物のタイトル	20th International Parallel and Distributed Processing Symposium, IPDPS 2006
出版社	IEEE Computer Society
ISBN（印刷版）	1424400546, 9781424400546
DOI	https://doi.org/10.1109/IPDPS.2006.1639431
出版ステータス	Published - 2006
イベント	20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006 - Rhodes Island, Greece 継続期間: 2006 4月 25 → 2006 4月 29

出版物シリーズ

名前	20th International Parallel and Distributed Processing Symposium, IPDPS 2006
巻	2006

Conference

Conference	20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006
国/地域	Greece
City	Rhodes Island
Period	06/4/25 → 06/4/29

ASJC Scopus subject areas

工学（全般）

文献へのアクセス

10.1109/IPDPS.2006.1639431

他のファイルとリンク

引用スタイル

Hasegawa, Y., Abe, S., Kurotaki, S., Tuan, V. M., Katsura, N., Nakamura, T., Nishimura, T., & Amano, H. (2006). Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. In 20th International Parallel and Distributed Processing Symposium, IPDPS 2006 Article 1639431 (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; Vol. 2006). IEEE Computer Society. https://doi.org/10.1109/IPDPS.2006.1639431

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. / Hasegawa, Yohei; Abe, Shohei; Kurotaki, Shunsuke その他.
20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 2006. 1639431 (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; Vol. 2006).

研究成果: Conference contribution

Hasegawa, Y, Abe, S, Kurotaki, S, Tuan, VM, Katsura, N, Nakamura, T, Nishimura, T & Amano, H 2006, Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. in 20th International Parallel and Distributed Processing Symposium, IPDPS 2006., 1639431, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006, vol. 2006, IEEE Computer Society, 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006, Rhodes Island, Greece, 06/4/25. https://doi.org/10.1109/IPDPS.2006.1639431

Hasegawa Y, Abe S, Kurotaki S, Tuan VM, Katsura N, Nakamura T その他. Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. In 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society. 2006. 1639431. (20th International Parallel and Distributed Processing Symposium, IPDPS 2006). doi: 10.1109/IPDPS.2006.1639431

@inproceedings{c400b1d220b24dee91ca0916f0372261,

title = "Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor",

abstract = "Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.",

author = "Yohei Hasegawa and Shohei Abe and Shunsuke Kurotaki and Tuan, {Vu Manh} and Naohiro Katsura and Takuro Nakamura and Takashi Nishimura and Hideharu Amano",

year = "2006",

doi = "10.1109/IPDPS.2006.1639431",

language = "English",

isbn = "1424400546",

series = "20th International Parallel and Distributed Processing Symposium, IPDPS 2006",

publisher = "IEEE Computer Society",

booktitle = "20th International Parallel and Distributed Processing Symposium, IPDPS 2006",

note = "20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006 ; Conference date: 25-04-2006 Through 29-04-2006",

}

TY - GEN

T1 - Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

AU - Hasegawa, Yohei

AU - Abe, Shohei

AU - Kurotaki, Shunsuke

AU - Tuan, Vu Manh

AU - Katsura, Naohiro

AU - Nakamura, Takuro

AU - Nishimura, Takashi

AU - Amano, Hideharu

PY - 2006

Y1 - 2006

N2 - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.

AB - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.

UR - http://www.scopus.com/inward/record.url?scp=33847103260&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847103260&partnerID=8YFLogxK

U2 - 10.1109/IPDPS.2006.1639431

DO - 10.1109/IPDPS.2006.1639431

M3 - Conference contribution

AN - SCOPUS:33847103260

SN - 1424400546

SN - 9781424400546

T3 - 20th International Parallel and Distributed Processing Symposium, IPDPS 2006

BT - 20th International Parallel and Distributed Processing Symposium, IPDPS 2006

PB - IEEE Computer Society

T2 - 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006

Y2 - 25 April 2006 through 29 April 2006

ER -

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

抄録

出版物シリーズ

Conference

ASJC Scopus subject areas

文献へのアクセス

他のファイルとリンク

フィンガープリント

引用スタイル