Perspective of low-power and high-speed wireless inter-chip communications for SiP integration

Performance gap between computation in a chip and communication between chips is widening. "System in a Package" (SiP) reduces chip distance significantly, enabling a high-speed and low-power interface. Electrical non-contact interfaces using inductive/capacitive coupling have advantages over mechanical interfaces employing Through Silicon Vias (TSV) and micro bumps. In this paper, a perspective of using wireless links between stacked chips in a package is presented. Techniques for high-speed and low-power data communications are discussed in various levels from signaling, circuit design, IC layout, and magnetic field design, as well as cross talk analysis and its countermeasures. A 1Tb/s 3W transceiver in 0.18μm CMOS is presented. Both clock and data are transmitted by inductive coupling. 1024 data transceivers are arranged with a pitch of 30μm. A 4-phases Time Division Multiple Access (TDMA) technique reduces crosstalk effectively. Measured Bit Error Rate (BER) is lower than 10^-13. Bi-Phase Modulation (BPM) is employed to improve noise immunity, resulting in power reduction.