TY - GEN
T1 - Power centric application mapping for dynamically reconfigurable processor array with Dual Vdd and Dual Vth
AU - Hironaka, Kazuei
AU - Amano, Hideharu
PY - 2011/12/1
Y1 - 2011/12/1
N2 - A coarse grained dynamically reconfigurable processor (CGDRP) with both Dual Vdd and Dual Vth is proposed with power centric Dual Vdd and Dual Vth assignment policies. The evaluation result shows that the Vth and Vdd assignment optimization algorithm reduces 37% of total consuming power within keeping the operational frequency.
AB - A coarse grained dynamically reconfigurable processor (CGDRP) with both Dual Vdd and Dual Vth is proposed with power centric Dual Vdd and Dual Vth assignment policies. The evaluation result shows that the Vth and Vdd assignment optimization algorithm reduces 37% of total consuming power within keeping the operational frequency.
KW - CGRA
KW - DRPA
KW - coarse grained dynamically reconfigurable device
KW - reconfigurable device
UR - http://www.scopus.com/inward/record.url?scp=84856893554&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84856893554&partnerID=8YFLogxK
U2 - 10.1109/ReConFig.2011.70
DO - 10.1109/ReConFig.2011.70
M3 - Conference contribution
AN - SCOPUS:84856893554
SN - 9780769545516
T3 - Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011
SP - 404
EP - 409
BT - Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011
T2 - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011
Y2 - 30 November 2011 through 2 December 2011
ER -