TY - GEN
T1 - SCIMA
T2 - 1999 International Workshop on Innovative Architectures, IWIA 1999
AU - Nakamura, Hiroshi
AU - Boku, Taisuke
AU - Okawara, Hideki
AU - Kondo, Masaaki
AU - Sakai, Shuichi
N1 - Publisher Copyright:
© 2000 IEEE.
PY - 1999
Y1 - 1999
N2 - Technological trends have brought the growing disparity between processor and memory speeds. This memory wall problem is becoming very serious especially in high performance computing. In this paper, we propose a new architecture SCIMA for solving this problem. In SCIMA, addressable memory is integrated into the processor chap besides ordinary cache. Since the on-chip memory i s software controllable, it has more ability to make good use of data locality than data cache which is controlled by hardware. The purpose of on-chip memory is to reduce the off-chip memory traffic by exploiting data reusability as much as possible within a chip. We have evaluated SCIMA by using QCD simulation, a practical application in quantum field theory. The performance evaluation reveals that SCIMA successfully reduces off-chip memory traffic and achieves higher performance than cache-only processor.
AB - Technological trends have brought the growing disparity between processor and memory speeds. This memory wall problem is becoming very serious especially in high performance computing. In this paper, we propose a new architecture SCIMA for solving this problem. In SCIMA, addressable memory is integrated into the processor chap besides ordinary cache. Since the on-chip memory i s software controllable, it has more ability to make good use of data locality than data cache which is controlled by hardware. The purpose of on-chip memory is to reduce the off-chip memory traffic by exploiting data reusability as much as possible within a chip. We have evaluated SCIMA by using QCD simulation, a practical application in quantum field theory. The performance evaluation reveals that SCIMA successfully reduces off-chip memory traffic and achieves higher performance than cache-only processor.
UR - http://www.scopus.com/inward/record.url?scp=85041524980&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85041524980&partnerID=8YFLogxK
U2 - 10.1109/IWIA.1999.898842
DO - 10.1109/IWIA.1999.898842
M3 - Conference contribution
AN - SCOPUS:85041524980
T3 - Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
SP - 45
EP - 53
BT - Innovative Architecture for Future Generation High-Performance Processors and Systems - 1999 International Workshop on Innovative Architectures, IWIA 1999
A2 - Nakashima, Hiroshi
A2 - Veidenbaum, Alex
PB - IEEE Computer Society
Y2 - 1 November 1999 through 3 November 1999
ER -