Sparse 3-D NoCs with inductive coupling

Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova

研究成果: Conference contribution

1 被引用数 (Scopus)


Wireless interconnects based on inductive coupling technology are compelling propositions for designing 3-D integrated chips. This work addresses the heat dissipation problem on such systems. Although effective cooling technologies have been proposed for systems designed based on Through Silicon Via (TSV), their application to systems that use inductive coupling is problematic because of increased wireless-communication distance. For this reason, we propose two methods for designing sparse 3-D chips layouts and Networks on Chip (NoCs) based on inductive coupling. The first method computes an optimized 3-D chip layout and then generates a randomized network topology for this layout. The second method uses a standard stack chip layout with a standard network topology as a starting point, and then deterministically transforms it into either a "staircase" or a "checkerboard" layout. We quantitatively compare the designs produced by these two methods in terms of network and application performance. Our main finding is that the first method produces designs that ultimately lead to higher parallel application performance, as demonstrated for nine OpenMP applications in the NAS Parallel Benchmarks.

ホスト出版物のタイトルProceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
出版社Institute of Electrical and Electronics Engineers Inc.
出版ステータスPublished - 2019 6月 2
イベント56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States
継続期間: 2019 6月 22019 6月 6


名前Proceedings - Design Automation Conference


Conference56th Annual Design Automation Conference, DAC 2019
国/地域United States
CityLas Vegas

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 制御およびシステム工学
  • 電子工学および電気工学
  • モデリングとシミュレーション


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