Stream applications on the dynamically reconfigurable processor

Masayasu Suzuki; Yohei Hasegawa; Yutaka Yamada; Naoto Kaneko; Katsuaki Deguchi; Hideharu Amano; Kenichiro Anjo; Masato Motomura; Kazutoshi Wakabayashi; Takao Toi; Toru Awashima

Stream applications on the dynamically reconfigurable processor

Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima

情報工学科

研究成果: Conference contribution

35 被引用数 (Scopus)

抄録

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

本文言語	English
ホスト出版物のタイトル	Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04
編集者	O. Diessel, J. Williams
ページ	137-144
ページ数	8
出版ステータス	Published - 2004 12月 1
イベント	2004 IEEE International Conference on Field-Programmable Technology, FPT '04 - Brisbane, Australia 継続期間: 2004 12月 6 → 2004 12月 8

出版物シリーズ

名前	Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

Other

Other	2004 IEEE International Conference on Field-Programmable Technology, FPT '04
国/地域	Australia
City	Brisbane
Period	04/12/6 → 04/12/8

ASJC Scopus subject areas

工学（全般）

他のファイルとリンク

引用スタイル

Suzuki, M., Hasegawa, Y., Yamada, Y., Kaneko, N., Deguchi, K., Amano, H., Anjo, K., Motomura, M., Wakabayashi, K., Toi, T., & Awashima, T. (2004). Stream applications on the dynamically reconfigurable processor. In O. Diessel, & J. Williams (Eds.), Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04 (pp. 137-144). (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

Stream applications on the dynamically reconfigurable processor. / Suzuki, Masayasu; Hasegawa, Yohei; Yamada, Yutaka その他.
Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. ed. / O. Diessel; J. Williams. 2004. p. 137-144 (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

研究成果: Conference contribution

Suzuki, M, Hasegawa, Y, Yamada, Y, Kaneko, N, Deguchi, K, Amano, H, Anjo, K, Motomura, M, Wakabayashi, K, Toi, T & Awashima, T 2004, Stream applications on the dynamically reconfigurable processor. in O Diessel & J Williams (eds), Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04, pp. 137-144, 2004 IEEE International Conference on Field-Programmable Technology, FPT '04, Brisbane, Australia, 04/12/6.

Suzuki M, Hasegawa Y, Yamada Y, Kaneko N, Deguchi K, Amano H その他. Stream applications on the dynamically reconfigurable processor. In Diessel O, Williams J, editors, Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. 2004. p. 137-144. (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

@inproceedings{9ee997aac0de4fa5b12b3c60dfa9bd30,

title = "Stream applications on the dynamically reconfigurable processor",

abstract = "Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.",

author = "Masayasu Suzuki and Yohei Hasegawa and Yutaka Yamada and Naoto Kaneko and Katsuaki Deguchi and Hideharu Amano and Kenichiro Anjo and Masato Motomura and Kazutoshi Wakabayashi and Takao Toi and Toru Awashima",

year = "2004",

month = dec,

day = "1",

language = "English",

isbn = "0780386515",

series = "Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04",

pages = "137--144",

editor = "O. Diessel and J. Williams",

booktitle = "Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04",

note = "2004 IEEE International Conference on Field-Programmable Technology, FPT '04 ; Conference date: 06-12-2004 Through 08-12-2004",

}

TY - GEN

T1 - Stream applications on the dynamically reconfigurable processor

AU - Suzuki, Masayasu

AU - Hasegawa, Yohei

AU - Yamada, Yutaka

AU - Kaneko, Naoto

AU - Deguchi, Katsuaki

AU - Amano, Hideharu

AU - Anjo, Kenichiro

AU - Motomura, Masato

AU - Wakabayashi, Kazutoshi

AU - Toi, Takao

AU - Awashima, Toru

PY - 2004/12/1

Y1 - 2004/12/1

N2 - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

AB - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

UR - http://www.scopus.com/inward/record.url?scp=20844447143&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=20844447143&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:20844447143

SN - 0780386515

T3 - Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

SP - 137

EP - 144

BT - Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

A2 - Diessel, O.

A2 - Williams, J.

T2 - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

Y2 - 6 December 2004 through 8 December 2004

ER -

Stream applications on the dynamically reconfigurable processor

抄録

出版物シリーズ

Other

ASJC Scopus subject areas

他のファイルとリンク

フィンガープリント

引用スタイル