TY - GEN
T1 - The evaluation of partial reconfiguration for a multi-board FPGA system FiCSW
AU - Yamakura, Miho
AU - Hironaka, Kazuei
AU - Azegami, Keita
AU - Musha, Kazusa
AU - Amano, Hideharu
N1 - Publisher Copyright:
© 2019 Copyright held by the owner/author(s).
PY - 2019/6/6
Y1 - 2019/6/6
N2 - FiC (Flow-in-Cloud) is a multi-FPGA system to realize a monolithic large FPGA image with multiple cost-efficient mid-range FPGAs connected withfl exible and high bandwidth interconnection network. The FPGA is used as both for computational resource and the network circuit switch, and separating FPGA regions by partial reconfiguration (PR) design technique. In this paper, we will introduce the FPGA design methodology with the PR technique for the FiC system. Evaluation result shows that the proposed design methodology reduces design and configuration time, and it enables to replace the region for computation without stopping the network running on the same FPGA.
AB - FiC (Flow-in-Cloud) is a multi-FPGA system to realize a monolithic large FPGA image with multiple cost-efficient mid-range FPGAs connected withfl exible and high bandwidth interconnection network. The FPGA is used as both for computational resource and the network circuit switch, and separating FPGA regions by partial reconfiguration (PR) design technique. In this paper, we will introduce the FPGA design methodology with the PR technique for the FiC system. Evaluation result shows that the proposed design methodology reduces design and configuration time, and it enables to replace the region for computation without stopping the network running on the same FPGA.
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U2 - 10.1145/3337801.3337805
DO - 10.1145/3337801.3337805
M3 - Conference contribution
AN - SCOPUS:85070557291
T3 - ACM International Conference Proceeding Series
BT - Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019
PB - Association for Computing Machinery
T2 - 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019
Y2 - 6 June 2019 through 7 June 2019
ER -